1. Field of the Invention
The invention relates to semiconductor fabrication, and more particularly to a method for fabricating a dual damascene structure.
2. Description of Related Art
A conventional method for fabricating a dual damascene structure typically includes simultaneously forming a via plug and a metal line in a dielectric layer. In more detail, a planarized dielectric layer is formed on a substrate, usually having a metal layer on top. According to a design, patterning the dielectric layer forms a via opening and a trench, in which the via opening exposes the metal layer below the dielectric layer, and the trench with wider width is formed over the via opening. A metal material is filled in the via opening and the trench so that a via plug filling the via opening and a metal line filling the trench are simultaneously formed. The via plug serves as a vertical coupling between two interconnecting metal layers, and the metal line, extending horizontally, is the upper interconnecting metal layer, which is electrically coupled to the lower interconnecting metal layer below the dielectric layer through the via plug. The formation of the via plug and the metal line further includes forming a metal layer over the substrate to fill the via opening and the trench and planarizing the metal layer to remove a portion of the metal layer other than the trench.
FIGS. 1A-1E are cross-sectional views of a portion of a substrate, schematically illustrating a convention fabrication process for forming a dual damascene structure.
FIG. 1A, a patterned metal layer 102 is formed on a substrate 100, which includes formed devices (not shown). The formation of the patterned metal layer 102 includes performing a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process to deposit a metal layer, and patterning the metal layer to form the patterned metal layer 102.
In FIG. 1B, a dielectric layer 106 is formed over the substrate 100. The dielectric layer 106 including silicon oxide has a typical dielectric constant of 4-4.9. A planarization process is performed to planarize the dielectric layer and to obtain a desired thickness.
In FIG. 1C, the dielectric layer 106 is patterned so as to form a dual damascene opening 107 in the dielectric layer 106 and expose the metal layer 102. The dual damascene opening 107 has a via opening 112 to expose the metal layer 102 and a trench 114 over the via opening so that the via opening 112 is exposed by the trench 114. The via opening 112 extends vertically but the trench 114 extends horizontally.
In FIG. 1D, a metal layer 118 is formed over the substrate 100 so that the via opening 112 and trench 114 of FIG. 1C, are also filled. In FIG. a chemical mechanical polishing (CMP) process is performed to remove a portion of the metal layer 118 other than the trench 114. So, the dielectric layer 106 is exposed. A remaining portion of the metal layer 118 simultaneously filling the via opening 112 and the trench 114 of FIG. 1C becomes a damascene metal line 120 including a via plug 118a and a metal line 118b. The via plug 118a fills the via opening 112 of FIG. 1C, and the metal line 118b fills the trench 114 of FIG. 1C. The metal line 118b is electrically coupled to the metal layer 102 through via plug 118a. A conventional dual damascene structure is formed.
In the conventional dual damascene structure, the dielectric layer 106 has the dielectric constant of 4-4.9, which is a typical quantity and is not small. When a device is fabricated in a highly reduced dimension, a line pitch between each the damascene metal line 120 is greatly reduce. The dielectric layer exits between each the damascene metal line 120 so that a parasitic capacitor is severely formed between each the damascene metal line 120. The parasitic capacitor causes a resistance-capacitance (RC) time delay. In addition, a cross talk phenomenon between the adjacent damascene metal line 120 also occurs. A device performance therefore is greatly degraded.